Designing Analog Chips

I doubt there are many people who could use this free book:

http:www.designinganalogchips.com

http://www.designinganalogchips.com/_count/designinganalogchips.pdf

for the titled purpose, actually designing an analog IC chip.  But there is a lot of good / interesting information in the book for the rest of us (at least in the first chapter which is as far as I've gotten :).  The author is Hans Camenzind, the designer of the famous 555 timer chip which is still in production / use even after decades:

https://en.wikipedia.org/wiki/Hans_Camenzind

As hams well know the 555 is the basis of numerous code practice oscillators and sidetone generators.

One thing in the book that reminded me of when I worked at GTE was when he mentions that an epitaxial or "epi" layer is often used in IC manufacturing to create a controlled substrate for the transistors on top of the silicon wafer.  The only reason why I remember this is that I remember a production meeting I attended as the IC test guy for an office system that GTE made.  The chips were CMOS (digital not analog) made by a captive GTE subsidiary called California Micro Devices (which oddly was located in Arizona :).  There were many problems with the chips but I remember one meeting where they were discussing reliability problems.  Since the system was for offices it was subject to carpet related static problems when the customers touched it or the equipment attached to it.  The CMOS chips could be triggered into latch-up by the static in the office during the winter.  Anyway, the discussion ended with someone saying:  "epi ?"  and everyone else (other than me) saying yes, epi.  Apparently California Micro Devices saved money by not buying wafers with an epitaxial layer or they couldn't grown their own in the process ?  But if an epitaxial wafer was used the chips were not subject to static triggered problems.  But it was just so funny to hear these guys sayin:  epi, epi, epi  :)

Best Regards,
Chuck, WB9KZY
http://wb9kzy.com/ham.htm